Modern integrated circuits utilize multiple clock signals that can be mutually asynchronous. Using mutually asynchronous clock signals can cause data corruption, especially when signals are sampled during an assertion period or during a negation period and especially before the level of a sampled signal is definite. It is known that sampling a signal that has an indefinite level can result in an unpredictable outcome. When a flip-flop samples an uncertain signal, it can enter a meta-stable state.
Prior art synchronizers include a sequence of at least two flip-flops, wherein the last flip-flop samples the output signal of the previous flip-flop. These flip-flips receive the same clock signal and there is a very low chance that all of these flip-flops will enter a meta-stable state. It is noted that this arrangement is robust but is area consuming and introduces a relatively long delay.